Recently, stackable multi-chip modules have been developed to give considerations of micro miniaturization and increased processing speed of electronic products.
U.S. Pat. No. 5,222,014 discloses a stackable multi-chip module, wherein an upper layer semiconductor package is stacked on and electrically connected with a lower layer semiconductor package thereof through solder joints or solder balls and by repeating the staking of the semiconductor packages, the performance and the processing speed of the module is increased without changing the size of the substrate. As shown in FIG. 7, since solder pads 700b on the lower surface 700a of the substrate 700 of the upper layer semiconductor package 70 are electrically connected to solder pads 710b on the upper surface 710a of the substrate 710 of the lower layer semiconductor package 71 through solder balls 72 disposed therebetween, the number of the solder pads 700b and 710b will affect the electrical connection between the upper layer semiconductor package 70 and the lower layer semiconductor package 71. That is, in the case of more I/O connections required for the semiconductor chip 701 of the upper layer semiconductor package 70, more solder pads 700b should be configured on the lower surface 700a of the substrate 700. However, more solder pads 700b are configured, size of the encapsulant 712 of the lower-layer semiconductor package 71 would be reduced, and accordingly size of the semiconductor chip 711 would also need to be reduced. Hence, size of the semiconductor chip 711 could be used for the lower layer semiconductor package 71 is restricted. From another point of view, if bigger-sized semiconductor chip 711 of the lower layer semiconductor package 71 is required, less solder pads 700b could be configured on the lower surface 700a of the substrate 700, and accordingly, the I/O connections of the upper layer semiconductor package 700 will be reduced, thus the type of the semiconductor package 700 could be used is restricted. In a word, choices of the chip of the stackable multi-chip module 7 will be affected by the number of solder pads and the types of semiconductor package, and thus the use of such a stackable multi-chip module is restricted.
Further, as the upper layer semiconductor package 70 and the lower layer semiconductor package 71 are electrically connected through the solder balls 72, the solder pads 710b of the lower layer substrate 710 cannot be too big, thereby, the height H of the solder balls will be limited. That is, height H of the solder balls has some limitation, which further limits height of the encapsulant 712 of the lower layer semiconductor package 71, generally under 0.3 mm.
According to above drawbacks, U.S. Pat. No. 6,828,665 (patentee is the same as that of the present patent application) discloses a semiconductor package that has a circuit board disposed in the encapsulant, wherein the solder pads of the circuit board being exposed from the encapsulant. Another semiconductor package can be stacked on and electrically connected to the circuit board of the semiconductor package through a plurality of solder balls. As shown in FIG. 8, a circuit board 80 having a plurality of solder pads 801 on top surface 800 thereof is soldered to and electrically connected to a substrate 83 through a plurality of solder balls 81, wherein the substrate 83 has a semiconductor chip 82 mounted thereon, and the semiconductor chip 82 is disposed between the circuit board 80 and the substrate 83. An encapsulant 84 encapsulating the semiconductor chip 82, the solder balls 81 and the circuit board 80 is formed on the substrate 83 with the solder pads 801 exposed from the encapsulant 84. Thus, another semiconductor package 8′ with a plurality of solder balls 85′ mounted on the bottom surface thereof can be stacked on the top surface 800 of the circuit board 80 and electrically connected to the semiconductor package 8 through the solder balls 85′ soldered to the solder pads 801 of the circuit board 80.
As the semiconductor chip 82 and the circuit board 80 are encapsulated by the encapsulant 84 at the same time, area of the bottom surface 802 of the circuit board 80 for mounting of the solder pads 803 will not be affected by size of the encapsulant 84. As a result, size and type of the semiconductor chip 82 can be selected more freely and layout of the solder pads 803 is more flexible compared with U.S. Pat. No. 5,222,014. However, during reflowing the solder balls 81 between the circuit board 80 and the substrate 83, as the semiconductor chip 82 of the semiconductor package 8 has not yet been encapsulated by the encapsulant, high temperature of the reflowing process can adversely affect quality of the bonding wires 86 electrically connecting the semiconductor chip 82 and the substrate 83. Meanwhile, the flux will contaminate the semiconductor chip 82 and the substrate 83. Therefore, reliability of the semiconductor package 8 is poor.
Accordingly, U.S. Pat. No. 6,861,288 discloses a semiconductor package which eliminates the need of solder balls for electrically connecting the substrate and the circuit board for stacking of another semiconductor package. As shown in FIG. 9, a metallic carrier 90 having supporting pins 901 is disposed on a substrate 91 for supporting a circuit board 92 on which another semiconductor package can be stacked. The circuit board 92 is supported by the metallic carrier 90 and located over the semiconductor chip 93. The metallic carrier 90 is attached to the semiconductor chip 93 through a spacer 94 made of thermally conductive glue or a film adhesive. The encapsulant 95 is formed on the substrate 91 and encapsulating the metallic carrier 90, the circuit board 92, the semiconductor chip 93, and the spacer 94. A part of the top surface 920 of the circuit board 92 is exposed from the encapsulant 95 such that solder pads 921 on that can be soldered together with solder balls 96′ of another semiconductor package 9′, thereby electrically connecting the semiconductor package 9′ with the semiconductor package 9 through the solder balls 96′. In addition, the semiconductor chip 93 of the semiconductor package 9 is electrically connected to the substrate 91 through a plurality of first bonding wires 97, and the circuit board 92 is electrically connected to the substrate 91 through a plurality of second bonding wires 98. For encapsulating the second bonding wires 98, the top surface 950 of the encapsulant 95 needs to be higher than exposed top surface 920 of the circuit board 92. Therefore, a concave 951 is formed on the top surface 920.
However, the metallic carrier 90 disposed on the semiconductor chip 93 complicates the packaging process and increases the cost. Meanwhile, there are multiple contacting interfaces, which are the surface-to-surface bonding of the circuit board 92 and the metallic carrier 90, the metallic carrier 90 and the spacer 94, and the spacer 94 and the semiconductor chip 93, in the semiconductor package 9, which can more easily result in delamination phenomenon in temperature cycle in fabrication process and in operating status of the semiconductor package, thus adversely affecting the quality and reducing the reliability of products. Further, as shown in FIG. 10, the mold M consisting the upper mold M1 and the lower mold M2 for forming the encapsulant 95 needs to have an insert portion in the upper mold M1 so as to form an encapsulant 95 completely encapsulating the second bonding wires 98 being higher than the exposed top surface 920 of the circuit board 92. The use of the specific upper mold M1 increases the fabrication cost.
Therefore, there is a need to provide a semiconductor package on which a semiconductor device can be stacked for solving the above problems.